The present invention relates generally to the manufacture of semiconductor wafers and more particularly, to a method of manufacturing semiconductor wafers that include protection from die tool induced crack propagation.
An individual integrated circuit or chip is usually formed from a larger structure known as a semiconductor wafer, which is usually comprised primarily of silicon, although other materials such as gallium arsenide and indium phosphide may be used. The semiconductor wafer includes a plurality of integrated circuits arranged in rows and columns with the periphery of each integrated circuit typically being square or rectangular in shape.
Typically, after fabrication the semiconductor wafer is sawn or “diced” into square or rectangular shaped discrete integrated circuits along two mutually perpendicular sets of parallel lines or streets lying between each of the rows and columns of integrated circuits. The singulated integrated circuits are typically referred to as die.
During the dicing process, the dicing tool can induce stresses on the semiconductor wafer that can lead to crack propagation through the dies. Crack propagation can severely damage, or at the very least degrade, the resultant integrated circuit.
Several methods have been devised for reducing dicing tool induced damage by crack propagation. For example, US 2006/0055002 describes a method in which a continuous seal ring, for blocking lateral movement of mobile ions, is implemented around metal layers that make up the film stack. According to US 2006/0055002, a shallow trench is also created beneath the surface of the silicon substrate by etching into a portion of the silicon substrate to circumscribe the seal ring. An oxide is then deposited into the etched trench to create a shallow trench isolator in the silicon substrate for reducing crack propagation through the silicon substrate. Although the method disclosed in US 2006/0055002 may reduce dicing tool induced crack propagation through the silicon substrate, the method addresses a different problem to the present invention in that the disclosed method does not address the problem of inter-layer delamination.
US 2005/0269720 discloses another method for providing crack protection for a silicon die. According to the method disclosed in US 2005/0269720, the wafer includes a nitride passivation layer that includes gaps along scribe streets to expose an oxide. A dicing tool can then cut along the scribe streets without producing cracks that propagate into die termination areas.
US 2005/0266661 discloses a semiconductor wafer that includes ditches in the scribe street. The ditches extend from the top surface of the wafer to the silicon substrate. According to US 2005/0266661, the disclosed arrangement of ditches is effective in preventing damage, such as chipping and cracking, at the chip edges. However, as with the other prior methods described earlier, the semiconductor wafer disclosed in US 2005/0266661 does not address the problem of dicing tool induced interlayer delamination between the layers deposited onto the silicon substrate.
It is an object of the present invention to provide a semiconductor manufacturing method that produces a semiconductor wafer incorporating improved protection against crack propagation and interlayer delamination caused by die separation.